A phase-locked loop (PLL) is a building block of local oscillator (LO) generation, clock generation and recovery, frequency synthesizers and other communications circuits. Some performance characteristics of a PLL may include the output phase noise, range of covered frequencies, tracking bandwidth, locking time, external spur rejection, and stability. The performance characteristics of a PLL may, at least in part, be determined by the PLL bandwidth. In some cases, a PLL may be designed or even optimized to operate at a certain point, e.g., with a specific known bandwidth and other parameters that may provide a specific performance, such as providing good noise immunity and spur rejection, etc.
A number of factors may vary or change, such as PLL operating frequency, semiconductor process, or environmental conditions such as supply voltage and temperature, that may impact or change the PLL bandwidth. Unfortunately, if a PLL bandwidth changes, the PLL performance may degrade or may even become unstable. Therefore, it may be desirable to provide a technique to calibrate or re-adjust a PLL bandwidth, e.g., to compensate for one or more varying factors or conditions.